1. Field of the Invention
The present invention relates to a drive circuit for a display device that displays an image by driving pixel TFTs arranged in a matrix. In particular, the present invention relates to an increase in the withstand voltage of the drive circuit of this type. Also, the present invention relates to a liquid-crystal display device and a liquid-crystal projector each having the drive circuit of this type.
2. Description of the Relate Art
In recent years, a technique by which a semiconductor device having a semiconductor thin film formed on an inexpensive glass substrate, for example, a thinfilm transistor (TFT) is fabricated has been rapidly developed. This is because a demand for active matrix liquid crystal display devices has been increased.
The active matrix liquid crystal display device is designed in such a manner that a TFT is disposed in each of several-ten to several-million pixel regions arranged in a matrix, and charges going in and out of the respective pixel electrodes are controlled by the switching function of the TFTs.
FIGS. 1A and 1B show the structure of a conventional active matrix liquid crystal display device. A shift register and a buffer circuit are generally called "peripheral drive circuit", and in recent years, they are formed integrally with an active matrix circuit on the same substrate.
In the active matrix circuit, there are thin film transistors using amorphous silicon formed on the glass substrate.
Also, there has been known a structure in which quartz is used as the substrate, and the thin film transistors are produced with polycrystal silicon films. In this case, the peripheral drive circuit and the active matrix circuit are structured by the thin film transistors formed on the quartz substrate.
Also, there has been known a technique by which a thin film transistor using a crystalline silicon film is produced on the glass substrate through a process such as laser annealing. The use of this technique makes it possible to integrate the active matrix circuit and the peripheral drive circuit on the glass substrate.
In the structure shown in FIGS. 1A and 1B, an image signal which is supplied to an image signal line is selected at a timing indicated by symbol (B) according to a signal from a shift register circuit (horizontal scanning shift register) in a source line side drive circuit. Then, a predetermined image signal is supplied to a corresponding source signal line.
The image signal supplied to the source signal line is selected by a thin film transistor of each pixel and written in a predetermined pixel electrode.
The thin film transistor of each pixel is operated according to a selected signal supplied to the thin film transistor from a shift register (vertical scanning shift register) in a gate line side drive circuit through a gate signal line.
This operation is sequentially repeated at appropriate timing according to the signals from the shift register in the source line side drive circuit and the signals from the shift register in the gate line side drive circuit, thereby allowing information to be sequentially written in each pixel disposed in a matrix.
After image information for one screen has been written in the respective pixels, image information for a succeeding screen is written. In this way, images are sequentially displayed. Normally, writing of information for one screen is conducted 30 or 60 times per one minute.
In recent years, display capacity has been increased, and display resolution has been highly fined with a rapid increase in information amount to be dealt with. Examples of the display resolution of a computer generally employed are indicated below with the number of pixels and standard names.
The number of pixels
(lateral x longitudinal): Standard name PA1 640.times.400:EGA PA1 640.times.480:VGA PA1 800.times.600:SVGA PA1 1024.times.768:XGA PA1 1280.times.1024:SXGA PA1 three power supplies Vdd1, Vdd2 and Vss; and PA1 a plurality of CMOS circuits formed on an insulating substrate, each of said plurality of CMOS circuits including: an output terminal; an input terminal; at least one p-channel TFT connected between said power supply Vdd2 and said output terminal; and an n-channel TFT having two gate electrodes connected between said output terminal and said Vss, PA1 an insulating substrate; PA1 a plurality of pixel TFTs formed on an insulating substrate; PA1 a drive circuit formed on the insulating substrate for driving the plurality of pixel TFTs; and PA1 a display medium an optical response of which is controlled by the plurality of pixel TFTs, PA1 wherein the drive circuit comprises: three power supplies Vdd1, Vdd2 and Vss; and a plurality of CMOS circuits formed on the insulating substrate, each of the plurality of CMOS circuits including: an output terminal; an input terminal; at least one p-channel TFT connected between the power supply Vdd2 and the output terminal; and an n-channel TFT having two gate electrodes connected between the output terminal and the Vss; and PA1 two power supplies Vdd and Vss; and PA1 a plurality of CMOS circuits formed on an insulating substrate, each of the plurality of CMOS circuits including: an output terminal; an input terminal; at least one p-channel enhancement TFT connected between the Vdd and the output terminal; an n-channel enhancement TFT at least one of a source and a drain of which is connected to the Vss; and an n-channel depletion TFT connected between the other of the source and the drain of the n-channel enhancement TFT and the output terminal, PA1 wherein a relation of the Vdd &gt;the Vss is satisfied, and a gate electrode of the n-channel depletion TFT is connected to a node between the n-channel depletion TFT and the n-channel enhancement TFT. PA1 an insulating substrate; PA1 a plurality of pixel TFTs formed on an insulating substrate; PA1 a drive circuit for driving the plurality of pixel TFTs; and PA1 a liquid crystal layer an optical response of which is controlled by the plurality of pixel TFTs, PA1 wherein the drive circuit comprises: two power supplies Vdd and Vss; and a plurality of CMOS circuits formed on the insulating substrate, each of said plurality of CMOS circuits including: an output terminal; an input terminal; at least one p-channel enhancement TFT connected between the Vdd and the output terminal; an n-channel enhancement TFT at least one of a source and a drain of which is connected to the Vss; and an n-channel depletion TFT connected between the other of the source and the drain of the n-channel enhancement TFT and the output terminal, and PA1 wherein a relation of the Vdd&gt;the Vss is satisfied, and a gate electrode of the n-channel depletion TFT is connected to a node between the n-channel depletion TFT and the n-channel enhancement TFT. PA1 three power supplies Vdd1, Vdd2 and Vss; PA1 a low-supply-voltage drive section; and PA1 a high-supply-voltage drive section, PA1 wherein a relation of the Vdd2&gt;the Vdd1&gt;the Vss is satisfied; PA1 wherein the high-supply-voltage drive section comprises: a plurality of CMOS circuits formed on an insulating substrate, each of the plurality of CMOS circuits including: an output terminal; an input terminal; at least one p-channel TFT connected between the power supplies Vdd2 and the output terminal; and an n-channel TFT having two gate electrodes connected between the output terminal and the Vss; and PA1 wherein one of said two gate electrodes of the n-channel TFr which is close to said p-channel TFT is connected to the Vdd1, and the other gate electrode is connected to the input terminal, and the Vdd1 is applied to a power supply of the low-supply-voltage drive section.
Also, in recent years, likewise in the field of personal computers, because software that conducts plural displays different in character on the display has spread, the display device is being shifted from the display device adaptive to VGA or SVGA standard to the display device adaptive to XGA or SXGA standard which is higher in display resolution.
Further, the above liquid crystal display device high in display resolution is being employed for display of a television signal in addition to display of a data signal in a personal computer.
Under the above circumstances, in recent years, projection type display devices using an active matrix liquid crystal panel, that is, projectors are rapidly being diffused on the market. The liquid crystal projector is designed to irradiate an intense light onto a liquid crystal panel and transcribe an image on a screen through a lens. The liquid crystal projector makes it possible to transcribe an image onto a screen of 100 or 200 inches due to its characteristic.
Also, the liquid crystal projector is excellent in color reproducibility more than the projector using a CRT, and also small in size, light in weight and low in power consumption.
As described above, in order to realize a liquid crystal panel or liquid crystal projector large in screen, high in fineness and high in resolution, the number of pixel TFTs to be used must be increased as much. In this case, a higher voltage than the conventional one must be applied to the gate signal line so that a desired voltage is applied to the gates of all TFTs on a selected row in the active matrix circuit.
FIG. 2 shows an example of a gate signal line side drive circuit (driver) in a liquid crystal display device which requires the application of a high voltage to the gate signal line. Reference numeral 201 denotes a shift register circuit; 202 is an invertor; 203 is a level shifter; and 204 is an invertor at a final stage. The invertor 204 at the final stage is connected to a corresponding gate signal line.
The shift register circuit is made up of a plurality of flip flop circuits. The shift register starts at a predetermined timing upon the input of a start pulse signal which is inputted to the shift register circuit. Also, a predetermined clock signal is inputted to the shift register. The shift register circuit has a function to supply a signal that determines an operation timing to a circuit corresponding to the gate signal line.
A signal from the shift register 201 is outputted to the invertor 202. The invertor 202 inverts the above inputted signal to output it to the level shifter 203.
An input signal of the level shifter 203 passes through the level shifter 203, thereby increasing in voltage, and then outputted to the invertor 204 at the final stage which is connected to the gate signal line. Thereafter, a signal inverted by the final-stage invertor 204 is outputted to the gate signal line.
In this example, two power supplies for the driver are required. In other words, a low-voltage power supply is used for the shift register 201 and the invertor 202, and a high-voltage power supply is used for the level shifter and the final-stage invertor 204, thus supplying a high-voltage signal to the gate signal line.
An example of circuits of the level shifter 203 and the invertor 204 conventionally used is shown in FIGS. 3A and 3B. A supply voltage Vddh of the level shifter 203 and the invertor 204 is 16 V. In FIG. 3B, in order to distinguish two n-channel TFTs for convenience of description, those TFTs are indicated by reference numeral 301 and 302, respectively.
The level shifter 203 is designed in such a manner that an inversion signal obtained by raising the voltage of the signal inputted to Vin is outputted from Vout. The signal outputted from Vout of the level shifter 203 is inputted to Vin of the final-stage invertor 204. The signal inputted to the final-stage invertor 204 is inverted and then outputted to a corresponding gate signal line from Vout.
FIG. 4 shows the results of simulating a change in the voltage of the final-stage invertor 204. In FIG. 4, symbol .largecircle. denotes supply voltage Vddh (=16V), symbol .DELTA. is an input signal Vin, symbol .gradient. is an output signal Vout, and symbol .quadrature. is a voltage Vx between the source and drain of two n-channel TFTs as shown in FIG. 3B. In FIG. 4, the axis of ordinates indicates the voltage values (V) of Vddh, Vout and Vx whereas the axis of abscissas indicates the voltage value (V) of Vin.
Also, FIG. 5 shows a waveform of the signal outputted from the final-stage invertor 204 to the gate signal line. In FIG. 5, the axis of ordinates indicates a voltage value (V), and the axis of abscissas indicates a time (.mu.s).
Upon studying the simulation result shown in FIG. 4, it is understood that when the input signal Vin is low, most of the supply voltage is applied to the n-channel TFT 301 because Vx is extremely smaller than Vout, and little voltage is applied to the n-channel TFT 302 (FIGS. 3A and 3B).
Hence, a load exerted on the n-channel TFT 301 is large, to thereby deteriorate the n-channel TFT 301.
This is caused by the phenomenon that in the case where a high voltage is applied to the TFT, the threshold value of the TFT, etc., fluctuates for accelerated hot carriers which are generated in a drain region and have a high energy, thereby inducing a change as a time elapses.
There has been known that the deterioration of the TFT due to the hot carriers is the largest when a gate-source voltage is close to 2V.
The above deterioration of the n-channel TFT 301 causes the supply of a signal to the gate signal line to be cut off, as a result of which there occurs display defects such as line defect, thereby degrading the image quality.
Also, in the above active matrix liquid crystal display device, drive of liquid crystal due to TN mode (twist nematic mode) is generally frequently employed. In the drive of liquid crystal due to the TN mode, nematic liquid crystal is orientated so as to be twisted by 90.degree.. Also, the twisted state is released by the application of a voltage to change an optical state. In the interior of the TN liquid crystal, such a phenomenon that the polarization axis of linear polarization rotates is used so that a desired image can be obtained by the linear polarization that passes through a pair of polarizing plates.
In the TN mode, liquid crystal can be driven at a low voltage such as several volts, and a load exerted on a peripheral drive circuit that drives the respective TFTs corresponding to several million pixels one by one is also relatively low. However, the TN mode suffers from a lot of defects such that the angle of view is narrow, a response speed is low, etc.
Under such existing circumstances, novel liquid crystal drive modes have been researched. In the novel modes, there are an electric field controlled birefringence (ECB) mode, a guest host mode, etc. In those modes, there is a mode that requires that a voltage higher than that in the TN mode is applied to liquid crystal. Likewise, this mode uses means for raising an output voltage from the invertor 202 by the level shifter 203 to output it to the final-stage invertor 204.
In this way, a case of applying a high voltage for driving liquid crystal also suffers from a problem such as the above-described deterioration of the TFT due to the hot carriers.